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19-0849; Rev 0; 7/07
10-Bit LVDS Serializer
General Description
The MAX9235 serializer transforms 10-bit-wide parallel LVCMOS/LVTTL data into a serial high-speed, low-voltage differential signaling (LVDS) data stream. The serializer typically pairs with deserializers like the MAX9206, which receives the serial output and transforms it back to 10-bit-wide parallel data. The MAX9235 transmits serial data at speeds up to 400Mbps over PCB traces or twisted-pair cables. Since the clock is recovered from the serial data stream, clock-to-data and data-to-data skew that would be present with a parallel bus are eliminated. The MAX9235 serializer requires no external components and no control signals and can lock to a 16MHz to 40MHz system clock. The serializer output is held in high impedance until the device is fully locked to the local system clock. The MAX9235 operates from a single +3.3V supply, is specified for operation from -40C to +105C, and is available in a 16-pin TQFN (3mm x 3mm) package.
Features
Stand-Alone Serializer (vs. SERDES) Ideal for Unidirectional Links Framing Bits for Deserializer Resync Allow Hot Insertion Without System Interruption LVDS Serial Output Rated for Point-to-Point Applications Wide Reference Clock Input Range 16MHz to 40MHz Low 31mA Supply Current 10-Bit Parallel LVCMOS/LVTTL Interface Up to 400Mbps Payload Data Rate Small 16-Pin TQFN (3mm x 3mm) Package
MAX9235
Ordering Information
PART MAX9235ETE+ PINPACKAGE 16 TQFN-EP* REF CLOCK RANGE (MHz) 16 to 40 PKG CODE TI633-5
Applications
Lane Departures Security Cameras Rear View Cameras Production Line Monitoring
+Denotes a lead-free package. Note: The device is specified over the -40C to +105C temperature range. *EP = Exposed pad. Pin Configuration and Functional Diagram appear at end of data sheet.
Typical Application Circuit
PARALLEL-TO-SERIAL OUT+ 100 OUTPCB OR TWISTED PAIR PLL IN+ 100 INSERIAL-TO-PARALLEL LVDS
OUTPUT LATCH
INPUT LATCH
10 IN_
10 OUT_
TCLK PLL TIMING AND CONTROL
REFCLK TIMING AND CONTROL CLOCK RECOVERY EN LOCK RCLK RCLK_R/F
MAX9235
MAX9206
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10-Bit LVDS Serializer MAX9235
ABSOLUTE MAXIMUM RATINGS
VCC to GND ........................................................-0.3V to +4.0V IN_, TCLK to GND ......................................-0.3V to (VCC + 0.3V) OUT+, OUT- to GND .............................................-0.3V to +4.0V Output Short-Circuit Duration.....................................Continuous Continuous Power Dissipation (TA = +70C) 16-Pin TQFN (derate 14.7mW/C above +70C) ......1177mW Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Operating Temperature Range .........................-40C to +105C Lead Temperature (soldering, 10s) .................................+300C ESD Protection (Human Body Model, OUT+, OUT-) ...........8kV ESD Protection (Human Body Model, IN_, TCLK) ...............2kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 50 1%, CL = 10pF, TA = -40C to +105C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER High-Level Input Voltage Low-Level Input Voltage Input Current LVDS OUTPUTS (OUT+, OUT-) Differential Output Voltage Change in VOD Between Complementary Output States Output Offset Voltage Change in VOS Between Complementary Output States Output Short-Circuit Current Power-Off Output Current POWER SUPPLY Supply Current ICC RL = 100 or 50 worst-case pattern (Figures 2, 4) 16MHz 40MHz 22 31 35 mA 45 SYMBOL VIH VIL IIN VIN_ = 0 or VCC RL = 100 RL = 50 CONDITIONS MIN 2.0 GND -20 600 250 735 370 1 RL = 100 RL = 50 1.025 1.125 1.265 1.265 3 -13 -10 TYP MAX VCC 0.8 +20 950 470 35 1.375 1.375 35 -15 +10 UNITS V V A
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, TCLK)
VOD VOD VOS VOS IOS IOX
Figure 1 Figure 1 Figure 1 Figure 1
mV mV V mV mA A
OUT+ or OUT- = 0, IN0 to IN9 = EN = high VCC = 0, OUT+ or OUT- = 0 or 3.6V
2
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10-Bit LVDS Serializer
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 50 1%, CL = 5pF, TA = -40C to +105C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Notes 2, 4)
PARAMETER TCLK Center Frequency TCLK Frequency Variation TCLK Period TCLK Duty Cycle TCLK Input Transition Time TCLK Input Jitter SWITCHING CHARACTERISTICS Low-to-High Transition Time High-to-Low Transition Time IN_ Setup to TCLK IN_ Hold from TCLK PLL Lock Time Bus LVDS Bit Width Serializer Delay tLHT tHLT tS tH tPL tBIT tSD Figure 7 tTCP / 6 Figure 4 Figure 4 Figure 5 Figure 5 Figure 6 RL = 100 RL = 50 RL = 100 RL = 50 1 3 2048 x tTCP tTCP / 12 (tTCP / 6) +5 2049 x tTCP 370 350 370 350 500 500 500 500 ps ps ns ns ns ns ns SYMBOL fTCCF TCFV tTCP TCDC tCLKT tJIT Figure 3 CONDITIONS MIN 16 -200 25 40 3 TYP MAX 40 +200 62.5 60 6 150 UNITS MHz ppm ns % ns ps (RMS)
MAX9235
TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VOD, VOD, and VOS. Note 2: CL includes scope probe and test jig capacitance. Note 3: Parameters 100% tested at TA = +25C. Limits over operating temperature range guaranteed by design and characterization. Note 4: AC parameters are guaranteed by design and characterization.
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10-Bit LVDS Serializer MAX9235
OUT+ VOD OUT-
RL 2 VOS RL 2
TCLK
ODD IN_ EVEN IN_
Figure 1. Output Voltage Definitions
Figure 2. Worst-Case ICC Test Pattern
90% TCLK 10%
90% 10%
3V
0
tCLKT
tCLKT
Figure 3. Input Clock Transition Time Requirement
5pF OUT+ 80% RL VDIFF OUT5pF tLHT VDIFF = (OUT+) - (OUT-) tHLT 20% 20% 80% VDIFF = 0
Figure 4. Output Load and Transition Times
tTCP
TCLK
1.5V
1.5V
1.5V
tS 1.5V
tH 1.5V
IN_
Figure 5. Data Input Setup and Hold Times 4 _______________________________________________________________________________________
10-Bit LVDS Serializer MAX9235
VCC
2.5V
2.5V
tPL
TCLK
OUT
HIGH IMPEDANCE
ACTIVE
HIGH IMPEDANCE
Figure 6. PLL Lock Time
IN
IN0-IN9 SYMBOL N
IN0-IN9 SYMBOL N + 1
tSD
TCLK
1.5V
START BIT OUT VDIFF = 0
OUT0-OUT9 SYMBOL N
STOP BIT START BIT
OUT0-OUT9 SYMBOL N + 1
STOP BIT
VDIFF = (OUT+) - (OUT-)
Figure 7. Serializer Delay
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10-Bit LVDS Serializer MAX9235
Typical Operating Characteristics
(VCC = +3.3V, RL = 50, CL = 5pF, TA = +25C, unless otherwise noted.)
WORST-CASE PATTERN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9205 toc01
34 33 SUPPLY CURRENT (mA) 32 31 30 29 TCLK = 40MHz 28 3.0 3.1 3.2 3.3 3.4 3.5
3.6
SUPPLY VOLTAGE (V)
PIN 1-7, 14, 15, 16 8 9, 12 10 11 13 --
NAME IN3-IN9, IN0, IN1, IN2 TCLK GND OUTOUT+ VCC EP
FUNCTION LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the rising TCLK edge. Each input is internally pulled to ground. LVCMOS/LVTTL Reference Clock Input. Accepts a 16MHz to 40MHz clock. TCLK provides a frequency reference to the PLL and strobes parallel data into the input latch on the rising edge. Ground Inverting Bus LVDS Differential Output Noninverting Bus LVDS Differential Output Power-Supply Input. Bypass to ground with a 0.1F capacitor and a 0.001F capacitor. Place the 0.001F capacitor closest to VCC. Exposed Pad. Solder EP to ground for improved heat dissipation.
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10-Bit LVDS Serializer
Detailed Description
The MAX9235 10-bit serializer transmits data over balanced media that may be a standard twisted-pair cable or PCB traces at 100Mbps to 400Mbps. The interface may be single- or double-terminated point-to-point. A double-terminated point-to-point interface uses a 100termination resistor at each end of the interface, resulting in a 50 load. The serializer requires a deserializer such as the MAX9206 for a complete data transmission application. A high-state start bit and a low-state stop bit, added internally, frame the 10-bit parallel input data and ensure a transition in the serial data stream. Therefore, 12 serial bits are transmitted for each 10-bit parallel input. The MAX9235 accepts a 16MHz to 40MHz reference clock, producing a serial data rate of 192Mbps (12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). Since only 10 bits are from input data, the actual throughput is 10 times the TCLK frequency. To transmit data, the serializer sequences through two modes: initialization mode and data transmission mode.
High-Impedance State
The serializer output pins (OUT+ and OUT-) are held in high impedance when VCC is first applied and while the PLL is locking to the local reference clock. If the serializer goes into high impedance, the deserializer loses PLL lock and needs to reestablish phase lock before data transfer can resume. This is done by transmitting all zeroes for at least one frame.
MAX9235
Applications Information
Power-Supply Bypassing
Bypass VCC with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC.
Differential Traces and Termination
Use controlled-impedance media and terminate at both ends of the transmission line in the media's characteristic impedance. Termination with a single resistor at the end of a point-to-point link typically provides acceptable performance. The MAX9235 output levels are specified for double-terminated point-to-point applications. With a single 100 termination, the output swing is larger. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. The differential output signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
Initialization Mode
When V CC is applied, the outputs are held in high impedance and internal circuitry is disabled by on-chip power-on-reset circuitry. When VCC reaches 2.35V, the PLL starts to lock to a local reference clock. The reference clock, TCLK, is provided by the system. The serializer locks within 2049 cycles of TCLK. Once locked, the serializer is ready to send data.
Data Transmission Mode
After initialization, input data at IN0-IN9 are clocked into the serializer by the TCLK input. Data strobes on the rising edge of TCLK. A start bit high and a stop bit low frame the 10-bit data and function as the embedded clock edge in the serial data stream. The serial rate is the TCLK frequency times the data and appended bits. For example, if TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) = 480Mbps. Since only 10 bits are from input data, the payload rate is 40 x 10 = 400Mbps.
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10-Bit LVDS Serializer MAX9235
Topologies
The MAX9235 can operate in point-to-point or broadcast topologies. A point-to-point connection terminated at each end in the characteristic impedance of the cable or PCB traces is shown in Figure 8. The total load seen by the serializer is 50. The double termination typically reduces reflections compared to a single 100 termination. A single 100 termination at the deserializer input is feasible and will make the differential signal swing larger. A point-to-point broadcast configuration is shown in Figure 9. The low-jitter MAX9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer connections. Since repeater jitter subtracts from the serializer-deserializer timing margin, a low-jitter repeater is essential in most high data rate applications.
Board Layout
For LVDS applications, a four-layer PCB that provides separate power, ground, and input/output signals is recommended. Separate LVTTL/LVCMOS and LVDS signals from each other to prevent coupling into the LVDS lines.
SERIALIZED DATA PARALLEL DATA IN 100 100 PARALLEL DATA OUT
MAX9235
MAX9206
Figure 8. Double-Terminated Point-to-Point
ASIC
ASIC
ASIC
MAX9206 MAX9235
MAX9206
100 100 100 100
MAX9150 REPEATER
100
100
Figure 9. Point-to-Point Broadcast Using MAX9150 Repeater 8 _______________________________________________________________________________________
10-Bit LVDS Serializer
Functional Diagram
GND
Pin Configuration
OUT+ OUTGND
MAX9235
TOP VIEW
PARALLEL-TO-SERIAL
12 OUT+ OUTIN0 14 IN1 15 VCC 13
11
10
9 8 7 TCLK IN9 IN8 IN7
IN_
10
INPUT LATCH
MAX9235
6 5
TCLK IN2 16 PLL TIMING AND CONTROL
+
1 IN3 2 IN4 3 IN5 4 IN6
MAX9235
THIN QFN 3mm x 3mm
Chip Information
PROCESS: CMOS
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10-Bit LVDS Serializer MAX9235
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 12x16L QFN THIN.EPS
L
MARKING
E E/2
(ND - 1) X e
(NE - 1) X e
D2/2
D/2 D
AAAA
C L
e D2
k
b E2/2
0.10 M C A B
C L
L
E2
0.10 C
0.08 C A A2 A1 L
C L
C L
e
e
PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
1 2
10
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10-Bit LVDS Serializer MAX9235
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PKG REF. A b D E e L N ND NE A1 A2 k 0.25 0 0.35
8L 3x3 MIN. NOM. MAX. 0.70 0.25 2.90 2.90 0.75 0.30 3.00 3.00 0.55 8 2 2 0.02 0.20 REF 0.25 0.05 0 0.80 0.35 3.10 3.10 0.75
12L 3x3 MIN. NOM. MAX. 0.70 0.20 2.90 2.90 0.45 0.75 0.25 3.00 3.00 0.55 12 3 3 0.02 0.20 REF 0.25 0.05 0 0.80 0.30 3.10 3.10 0.65
16L 3x3 MIN. NOM. MAX. 0.70 0.20 2.90 2.90 0.30 0.75 0.25 3.00 3.00 0.40 16 4 4 0.02 0.20 REF 0.05 0.80 0.30 3.10 3.10 0.50 PKG. CODES TQ833-1 T1233-1 T1233-3 T1233-4 T1633-2 T1633F-3 T1633FH-3 T1633-4 T1633-5
EXPOSED PAD VARIATIONS
D2 MIN. 0.25 0.95 0.95 0.95 0.95 0.65 0.65 0.95 0.95 NOM. 0.70 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 1.25 MIN. 0.25 0.95 0.95 0.95 0.95 0.65 0.65 0.95 0.95 E2 NOM. 0.70 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 1.25 PIN ID 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.225 x 45 0.225 x 45 0.35 x 45 0.35 x 45 JEDEC WEEC WEED-1 WEED-1 WEED-1 WEED-2 WEED-2 WEED-2 WEED-2 WEED-2
0.65 BSC.
0.50 BSC.
0.50 BSC.
NOTES: 1. 2. 3. 4. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. N IS THE TOTAL NUMBER OF TERMINALS. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. DRAWING CONFORMS TO JEDEC MO220 REVISION C. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. WARPAGE NOT TO EXCEED 0.10mm.
5. 6. 7. 8. 9. 10. 11. 12.
PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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